New Graduate Engineer - ASIC Design

5w1 month ago

SpaceX

Hawthorne, US · Full-time · $125,000 – $150,000

About this role

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. As a New Graduate Engineer on the Starshield team, you will be developing cutting-edge next-generation FPGAs and ASICs for deployment in space and ground infrastructures around the globe.

In this role, you will design digital ASICs and/or FPGAs, evaluate architectural trade-offs based on features and performance requirements, and derive specifications for subsystems and circuits. You will work with modem/DSP and RFIC engineers to partition functions between hardware and software domains, define micro-architecture, implement RTL in Verilog/System Verilog, and deliver fully verified, synthesis/timing clean designs.

You will work in a highly collaborative and fast-paced environment, exploring unsolved problems and applying the SpaceX mindset of iterating rapidly to go from design and demo to operational capability at lightning pace. You will also participate in silicon bring-up and validation, and assist in the development of automated test lab equipment for lab measurements.

This role offers the opportunity to contribute to advanced development programs in support of U.S. National Security, leveraging SpaceX’s Starlink technology and launch capability. You will be challenged to learn new skills and work on unsolved problems in a dynamic environment with changing needs and requirements.

Requirements

Bachelor’s degree in electrical engineering, computer engineering, or computer science.
Graduating with a bachelor’s degree, master’s degree, or PhD in 2026 or 2027.
1+ years of experience in RTL implementation and/or FPGA/ASIC development.
Experience solving problems including clock domain crossings and power optimization.
Experience developing complex ASICs.
Experience with multicore CPU subsystem design and standard bus protocols (e.g. AXI, AHB).
Scripting skills (Python, TCL, etc.) and experience with EDA tools such as HDL simulators (e.g. VCS, Questa, IES) and FPGA tools (e.g. Xilinx Vivado, Altera Quartus II).
Ability to work in a dynamic environment with changing needs and requirements, and a team-player, can-do attitude.

Responsibilities

Design digital ASICs and/or FPGAs for Starshield projects.
Evaluate architectural trade-offs based on features, performance requirements, and system limitations.
Derive specifications for subsystems and circuits, and work with modem/DSP and RFIC engineers to partition functions between hardware and software domains.
Define micro-architecture, implement RTL in Verilog/System Verilog, integrate at top level, and deliver fully verified, synthesis/timing clean designs.
Work closely with the verification team to ensure all aspects of the design are covered and verified.
Provide timing constraints for IPs and support the physical implementation team (synthesis, timing closure, formality check).
Participate in silicon bring-up and validation, and assist in the development of automated test lab equipment for lab measurements.

Benefits

Pay range: $125,000.00 - $150,000.00 (Level I).
Opportunity to work on advanced development programs in support of U.S. National Security.
Access to cutting-edge next-generation FPGA and ASIC technologies for space and ground infrastructure.
Fast-paced, collaborative environment with rapid iteration from design to operational capability.